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MRF89XA
FIGURE 2-18:
MRF89XA REGISTERS MEMORY MAP
Register Name
Register Name
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
GCONREG
DMODREG
FDEVREG
BRSREG
FLTHREG
FIFOCREG
R1CREG
P1CREG
S1CREG
R2CREG
P2CREG
S2CREG
PACREG
FTXRXIREG
FTPRIREG
RSTHIREG
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
FILCREG
PFCREG
SYNCREG
RSTSREG
RSVREG
OOKCREG
SYNCV31REG
SYNCV23REG
SYNCV15REG
SYNCV07REG
TXCONREG
CLKOREG
PLOADREG
NADDSREG
PKTCREG
FCRCREG
The MRF89XA registers functionally handles
command, configuration, control, status or data/FIFO
fields as listed in Table 2-6 . The registers operate on
parameters common to transmit and receive modes,
Interrupts, Sync pattern, crystal oscillator and packets.
The FIFO serves as a buffer for data transmission and
reception. There is a shifted register (SR) to handle bit
shifts for the FIFO during transmission and reception.
POR sets default values in all Configuration/Control/
Status registers.
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 27
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